View INTELPENTIUMCPU_2897984.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) january 1998 order number:243515-002 n intel pentium? processor with mmx? technology on .25 micron running at 166/200/233/266 mhz n second-level cache of pipeline burst sram ? burst read/write at 3-1-1-1; back-to-back burst reads at 3-1-1-1-1-1-1-1 ? supports up to 64mb of cacheable system memory (non-pci memory) n supports zz snooze mode power management n processor core voltage regulation supports input voltages ? 5v to 20v at or above 85% peak efficiency ? all cpu and i/o ring voltages supplied by the module. n thermal transfer plate for heat dissipation n intel 430tx pciset system controller ? dram controller supports edo and sdram at 3.3v ? provides pci clkrun# signal to control memory clock on the pci bus ? sdram clock enable support and self refresh of edo or sdram during suspend mode ? compatible smram (c_smram) and extended smram (e_smram) modes of power management; e_smram mode supports write-back cacheable smram up to 1mb ? 3.3v pci bus control, rev 2.1 compliant n active thermal feedback (atf) sensing ? internal a/d - digital signaling (smbus) across the module interface ? programmable trip point interrupt or poll mode for reading temperature the intel pentium? processor with mmx? technology 166/200/233/266 mhz mobile module is a small, highly integrated assembly containing an intel mobile processor and its immediate system-level s upport. specifically, the power supply for the processor's unique voltage requirements, the system level 2 cache memory and the core logic required to bridge the processor to the standard system buses are on the m odule. the module interfaces electrically to its host system via a 3.3-volt pci bus, a 3.3-volt memory bus, and 2.5-volt intel 430tx pciset control signals. intel pentium? processor with mmx? technology mobile module on .25 micron
1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liab ility whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liab ility or warranties relating to fitness for a particular purpose, merc hantab ility, or infri ngement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsib ility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel mobile module may contain design defects or errors known as errata. current characterized errata are available on request. mpeg is a international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725 or by visiting intels website at http://www.intel.com copyright ? intel corporation1997. * third-party brands and names are the property of their respective owners.
intel pentium? processor with mmx? technology mobile module 3 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) contents page page 1.0. introduction.............................................. 4 1.1. a rchitecture o verview ............................. 4 1.2. i ntel m obile m odule r evision i dentification .............................................. 5 2.0. module connector interface .......... 6 2.1. s ignal d efinitions ...................................... 6 2.1.1. memory (108 signals)..................... 7 2.1.2. pci (56 signals)................................. 8 2.1.3. processor/piix4 isa bridge sideband (9 signals) .................... 10 2.1.4. power management (8 signals)........................................ 11 2.1.5. clock (8 signals) .......................... 12 2.1.6. voltages (39 signals) ................. 13 2.1.7. itp/jtag (7 signals)....................... 14 2.1.8. miscellaneous (44 signals)...... 15 2.2. c onnector p in a ssignments ................... 16 2.3. c onnector f ootprint .............................. 18 2.3.1. pin and pad assignment............. 18 2.4. c onnector s pecifications ...................... 19 3.0. functional description...................... 20 3.1. i ntel m obile m odule ................................. 20 3.2. l2 c ache .................................................... 20 3.3. 430tx pci set s ystem c ontroller ......... 20 3.3.1. memory organization................ 21 3.3.2. 64-mbit sdram support...............21 3.3.3. pci interface..................................22 3.4. p rocessor c ore v oltage r egulation ................................................23 3.4.1. voltage regulator efficiency........................................23 3.4.2. voltage regulator control............................................24 3.4.3. voltage signal definition and sequencing.....................................25 voltage plane sequencing...................26 3.5. a ctive t hermal f eedback ........................26 3.6. t hermal t ransfer p late ..........................27 3.7. m odule t hermal r esistance ...................27 4.0. mechanical requirements................27 4.1. m odule d imensions ...................................27 4.1.1. board area .....................................27 4.1.2. printed circuit board thickness...................................................30 4.1.3. height restrictions ...................30 4.2. m odule p hysical s upport .......................32 4.3. m odule m ounting r equirements ...........32 4.4. m odule p roduct t racking c ode ............34 5.0. environmental standards................35
intel pentium? processor with mmx? technology mobile module 4 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 1.0. introduction the intel pentium ? processor with mmx? technology mobile module is the fundamental building block for a system m anufacturer to incorporate into a notebook system. the intel mobile module incorporates an intel pentium processor with mmx technology mobile processor, second- level cache, intel 430tx pciset northbridge system contr oller, voltage regulator, and thermal sensor on a single printed circuit board. intels pciset architecture allows for physical partitioning at both the pci and dram interfaces; therefore the electrical interconnect defined for the intel mobile module includes the pci bus, dram memory bus and some pciset sideband signals. an onboard voltage regulator provides the dc conversion from the system m anufacturers dc voltage to the processors core voltage and the 2.5v cpu interface signals. this isolation of the processor voltage requirements allows the system manufacturer to incorporate intel mobile modules with different processor variants into a notebook system. building around this modular design gives the system m anufacturer these advantages: avoids complexities associated with designing high-speed processor core logic boards no requirement for manufacturing capabilities of tape carrier package (tcp) processors future intel mobile modules provide an upgrade path for notebook designs using a standard interface eliminates the need to design for unique voltage requirements over succeeding generations of processors. the 430tx pciset (northbridge) is one of two physical vlsi devices that constitute the intel 430tx pciset controller. the second 430tx device (southbridge) is known as the piix4 isa bridge. the manufacturers system electronics, which connects to the intel mobile module, must include a piix4 isa bridge device. the piix4 isa bridge provides extensive power management capabilities and is designed to support both the 430tx pciset for current mobile pentium processors and the next northbridge device for the next generation of intel mobile processors. 1.1. architecture overview the intel mobile module is a small, highly integrated assembly containing the pentium processor with mmx technology 166/200/233/266 mhz mobile processor with internal/bus frequencies of 166/66, 200/66, 233/66, and 266/66 mhz and its immediate system-level s upport. the module interfaces electrically to its host system via a 3.3v pci bus, a 3.3v memory bus, 2.5v cpu interface signals, and the intel 430tx pciset system contr oller. the intel mobile module includes a second-level cache of pipeline burst sram with capabilities to burst read/write at 3-1-1-1 and back-to-back burst reads at 3-1-1-1-1-1-1-1. the module supports up to 64 mb of cacheable system memory ( non-pci memory) and zz snooze mode power management. the intel mobile module contains key features of the intel 430tx pciset system contr oller. the dram controller supports edo at 3.3v with a burst read at 5-2-2-2 (60ns) and sdram at 3.3v with a burst read at 6-1-1-1 (66 mhz, cl=2). the system contr oller provides a pci clk run# s ignal to control memory clock on the pci bus as well as the internal clock control (also known as chip standby or gated clock). the sdram clock enables support and self refresh of edo or sdram during suspend mode and is fully compatible smram (c_smram) and extended smram (e_smram) modes of power management; e_smram mode supports write-back cacheable smram up to 1 mb. the intel 430tx pciset system contr oller is a 3.3v pci bus control which is compliant with pci rev 2.1 specifications. the processor core voltage regulation supports input voltages from 5v to 20v (+5 percent) enabling at or above 85 percent peak efficiencies and de-couples processor voltage requirements from the system. the intel mobile module incorporates active thermal feedback (atf) sensing which is acpi rev 1.0 compliant by including an internal a/d - digital signaling (smbus) across the module interface and a programmable trip point interrupt or poll mode for reading temperature.
intel pentium? processor with mmx? technology mobile module 5 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) a thermal transfer plate for heat dissipation from the processor provides a standard thermal attach point to which the system m anufacturer connects a system heat pipe and heat spreader plate. figure 1 illustrates the block diagram of the intel mobile module. 1.2. intel mobile module revision identification the intel mobile module provides four dedicated connector pins for the sole purpose of identifying the revisions. these four pins allow up to 16 unique revision levels. the system electronics can use these pins to determine a particular revision level of an intel mobile module. system manufacturer software can query these revision id bits, along with the 430tx pciset, to provide complete revision level identification. vcpuio processor voltage regulator atf sense pentium ? processor w/mmx? technology host bus 430tx pciset "northbridge" tag pb sram memory bus 280-pin board-to-board connector pci bus pclk_5 processor core voltage i 2 c in-target probe debug signals hclk_1 hclk_0 piix4 sidebands 5v-21v mmo_001 figure 1. block diagram for the intel mobile module
intel pentium? processor with mmx? technology mobile module 6 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.0. module connector interface 2.1. signal definitions the intel mobile module connector signals are defined with the intention of supporting future modules. table 1 provides a list of signals by category and the corresponding number of signals in each category. table 1. module connector signal summary signal group number memory 108 pci 56 processor/piix4 isa bridge sideband 9 power management 8 clocks 8 voltage: v_dc 10 voltage: v_3s 20 voltage: v_5 1 voltage: v_3 5 voltage: v_cpuio 3 itp/jtag 7 misc. & module id 5 ground 32 reserved 7 total 280
intel pentium? processor with mmx? technology mobile module 7 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.1. memory (108 signals) table 2 lists the intel mobile module memory interface signals. some signals are defined as reserved for future use. table 2. memory signal descriptions name type voltage description mpd[7:0] i/o v_3s memory parity data: these signals connect to the dram parity. these pins are not implemented in the 430tx pciset and are reserved. *ras[5:0]# or cs[5:0]# o v_3s row address strobe (edo): these pins select the dram row. chip select (sdram): these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. *cas[7:0]# or dqm[7:0] o v_3s column address strobe (edo): these pins select the dram column. input/output data mask (sdram): these pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle. *ma[13:0] o v_3s memory address (edo/sdram): this is the row and column address for dram. these buffers now include programmable size selection, as controlled by the dramec[mad] bit. the 430tx pciset implements (and the intel mobile module supports) only ma[13:0]. see figure 3 for more details. *mwe[a,b]# o v_3s memory write enable (edo/sdram): mwe[a,b]# should be used as the write enable for the memory data bus. each copy is intended to support four rows, for loading purposes. *sras[a,b]# o v_3s sdram row address strobe (sdram): when active low, this signal latches row address on the positive edge of the clock. this signal also allows row access and pre-charge. each copy is intended to support four rows, for loading purposes. the srasa signal is used to configure the mobile mode of the 430tx pciset. when the rst# signal is active, srasa is an input. the intel mobile module has a pull-down resistor so that srasa is sampled low at the rising edge of rst#; thereby configuring the 430tx pciset in mobile mode. *scas[a,b]# o v_3s sdram column address strobe (sdram): when active low, this signal latches column address on the positive edge of the clock. this signal also allows column access. each copy is intended to support four rows, for loading purposes. *cke[a,b]# o v_3s sdram clock enable (sdram): sdram clock enable pin. when these signals are de-asserted, sdram enters power-down mode. each copy is intended to support four rows, for loading purposes. md[63:0] i/o v_3s memory data: these signals are connected to the dram data bus. they are not terminated on the intel mobile module and it is recommended that the system electronics provide series termination of 33 w . * - these signals are terminated with a 22 w series resistor on the intel mobile module.
intel pentium? processor with mmx? technology mobile module 8 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.2. pci (56 signals) table 3 lists the intel mobile modules pci interface signals. table 3. pci signal descriptions name type voltage description ad[31:0] i/o v_3s address/data: the standard pci address and data lines. the address is driven with frame# assertion, and data is driven or received in following clocks. c/be[3:0]# i/o v_3s command/byte enable: the command is driven with frame# assertion, and byte enables corresponding to supplied or requested data are driven on following clocks. frame# i/o v_3s frame: assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. devsel# i/o v_3s device select: this signal is driven by the 430tx pciset when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o v_3s initiator ready: asserted when the initiator is ready for data transfer. trdy# i/o v_3s target ready: asserted when the target is ready for a data transfer. stop# i/o v_3s stop: asserted by the target to request the master to stop the current transaction. lock# i/o v_3s lock: used to establish, maintain and release resource locks on pci. req[3:0]# i v_3s pci request: pci master requests for pci. gnt[3:0]# o v_3s pci grant: permission is given to the master to use pci. *phold# i v_3s pci hold: this signal comes from the expansion bridge; it is the bridge request for pci. the 430tx pciset will drain the dram write buffers, drain the processor-to-pci posting buffers, and acquire the host bus before granting the request via phlda#. this ensures that gat timing is met for isa masters. the phold# protocol has been modified to include support for passive release. *phlda# o v_3s pci hold acknowledge: this signal is driven by the 430tx pciset to grant pci to the expansion bridge. the phlda# protocol has been modified to include support for passive release. par i/o v_3s parity: a single parity bit is provided over ad[31:0] and c/be[3:0]
intel pentium? processor with mmx? technology mobile module 9 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) *serr# o v_3s system error: this signal is driven low by any pci device that detects a system error. it is not implemented in the 430tx pciset, however to maintain compatibility with future modules a pull up is required. *clkrun# i/o v_3s clock run: an open-drain output and also an input. the 430tx pciset requests the central resource (piix4 isa bridge) to start or maintain the pci clock by asserting clkrun#. the 430tx pciset tri-states clkrun# upon de-assertion of reset. an external 8.2k w to 10k w pull up resistor is required. pci_rst# i v_3s reset: this signal asynchronously resets the 430tx pciset. the pci signals also tri-state, compliant with pci rev 2.0 and 2.1 specifications. * - these signals are open-drain and require a pull up resistor on the system electronics.
intel pentium? processor with mmx? technology mobile module 10 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.3. processor/piix4 isa bridge sideband (9 signals) table 4 lists the intel mobile modules processor and piix4 isa bridge sideband signals at the connector interface. (refer to the piix4 isa bridge external architecture specification (order number 290562-001) for complete signal descriptions and detailed functions.) the voltage level for these signals is determined by v_cpuio, which is supplied by the intel mobile module. table 4. processor/piix4 isa bridge sideband signal descriptions name type voltage description ferr# o v_cpuio numeric coprocessor error: this pin functions as a ferr# signal supporting coprocessor errors. this signal is tied to the coprocessor error signal on the processor and is driven by the processor to the piix4 isa bridge. note: this signal does not require a pull up on the system electronics. a pull up is present on the intel mobile module. *cpurst i v_cpuio processor reset: the piix4 isa bridge asserts cpurst to reset the processor. the piix4 isa bridge asserts cpurst# during power-up and when a hard reset sequence is initiated through the rc register. *ignne# i v_cpuio ignore error: this signal is connected to the ignore error pin on the processor and is driven by the piix4 isa bridge. *init# i v_cpuio initialization: init is asserted by the piix4 isa bridge to the processor for system initialization. note: the system m anufacturer should provide a pull up/pull down option on this pin, and connect this piix4 isa bridge input to the intel mobile module connector pin bb38. *intr i v_cpuio processor interrupt: intr is driven by the piix4 isa bridge to signal the processor that an interrupt request is pending and needs to be serviced. *nmi i v_cpuio non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the piix4 isa bridge generates an nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. *a20m# i v_cpuio address bit 20 mask: when enabled, this causes the processor to emulate the address wraparound at one mbyte which occurs on the intel 8086 processor. *smi# i v_cpuio system management interrupt: smi# is an active low synchronous output that is asserted by the piix4 isa bridge in response to one of many enabled hardware or software events. the smi# signal can be an asynchronous input to the processor. however, in this chip set smi# is synchronous to pclk. *stpclk# i v_cpuio stop clock: stpclk# is an active low synchronous output that is asserted by the piix4 isa bridge in response to one of many hardware or software events. stpclk# connects directly to the processor and is synchronous to pclk. when the processor samples stpclk# asserted it responds by stopping its internal clock. * - these signals are open-drain and require a pull up resistor on the system electronics.
intel pentium? processor with mmx? technology mobile module 11 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.4. power management (8 signals) table 5 lists the intel mobile modules power management signals. the sm_clk and sm_data signals refer to the two-wire serial smbus interface. although this interface is currently used solely for the digital thermometer thermal sensor, there are reserved serial addresses for future use. table 5. power management signal descriptions name type voltage description *oem_pu i v_3 oem pull-up: a pull up resistor of 10k w is required on oem_pu. l2_zz i v_3 low-power mode for cache sram: this pin is used to power down the l2 cache srams . see piix4 isa bridge external architecture specification (order number 290562-001) on zz. sus_stat# i **v_3al- ways suspend status: this signal connects to the sus_stat1# output of the piix4. it provides information on the host clock status and is asserted during all suspend states.. vr_on i v_3s vr_on: voltage regulator on. this 3.3v signal controls the operation of the intel mobile modules voltage regulator. this signal should be generated as a function of the piix4 susb# signal. vr_on should be timed to rise after the switch power planes have stabilized. please refer to section 3.4.2 for proper vr_on sequencing. vr_pwrgd o v_3s vr_pwrgd: driven by the intel mobile module to indicate the voltage regulator is stable. can be used in some combination to generate the system pwrok signal. caution : this signal has an output impedance of approximately 100k w . care must be taken to prevent loading of this signal. sm_clk i v_3 serial clock: clock signal used on the smbus - smbus interface to the digital thermometer. sm_data i/o v_3 serial data: data signal on the smbus - smbus interface to the digital thermometer. *atf_int# o v_3 atf interrupt: output signal of the digital thermometer. see national semiconductor lm75 specification for pull up values. * - these signals are open-drain and require a pull up resistor on the system electronics. ** - v_3always is the 3.3v continuous supply. this voltage is generated whenever v_dc is available and supplied to the piix4 resume well.
intel pentium? processor with mmx? technology mobile module 12 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.5. clock (8 signals) table 6 lists the intel mobile modules clock signals. table 6. clock signal descriptions name type voltage description *oem_pd i v_3 oem pull-down: a pull-down resistor of 1k w is required on oem_pd. pclk i v_3s pci clock in: pclk is an input to the intel mobile module from the ckdm66-m clock source and is one of the systems pci clocks. this clock is used by all of the 430tx pciset logic in the pci clock domain. this clock is stopped when the piix4 isa bridge pci_stp# signal is asserted. hclk[1:0] i v_cpuio host clock in: these pins are used solely for ckdm66-m host clocking. this clock is used by the processor, 430tx pciset and l2. this clock is stopped when the piix4 isa bridge pci_stp# signal is asserted. susclk i v_3 suspend clock: 32 khz input for dram refresh circuitry and clocking events in suspend state. the dram refresh during suspend and non- suspend states is performed based on this clock. fqs[1:0] 0 v_3s frequency status: provides status of the host clock frequency to the system electronics. these signals are static and are pulled either low or high to the v_3s voltage. fqs1 fqs0 frequency 0 0 60 mhz 0 1 66 mhz 1 0 reserved 1 1 reserved cpu3.3_2.5# o v_cpuio clock voltage select: provides status to the system electronics about the voltage level at which the ckdm66-m clock generator should be operating. * - this signal requires a pull down resistor on the system electronics.
intel pentium? processor with mmx? technology mobile module 13 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.6. voltages (39 signals) table 7 lists the intel mobile modules voltage signal definitions. table 7. voltage descriptions name type number description v_dc i 10 dc input: 5 - 20v +5% v_3s i 20 susb# controlled 3.3v: power-managed 3.3 voltage supply. an output of the voltage regulator on the system electronics. this rail is off during str, std, and soff. v_5 i 1 susc# controlled 5v: power-managed 5.0 voltage supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. note : v_5s can be used as a susb# controlled voltage supply. v_3 i 5 susc# controlled 3.3v: power-managed 3.3 voltage supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_cpuio o 3 processor i/o ring: driven by the intel mobile module to power processor interface signals such as the piix4 isa bridge open-drain pull ups for the processor/piix4 isa bridge sideband signals.
intel pentium? processor with mmx? technology mobile module 14 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.7. itp/jtag (7 signals) table 8 lists the intel mobile modules in-target probe (itp)/jtag signals, which the system electronics can use to implement a processor debug port. the system m anufacturer can use debug port signals on development-level boards, or on production boards for manufacturing testability. please check with your local intel sales representative for further details on recommendations and requirements for a debug port. table 8. itp/jtag pins name type voltage description *tdo o v_cpuio jtag test data out: serial output port. tap instructions and data are shifted out of the processor from this port. *tdi i v_cpuio jtag test data in: serial input port. tap instructions and data are shifted into the processor from this port. *tms i v_cpuio jtag test mode select: controls the tap controller change sequence. *tclk i v_cpuio jtag test clock: testability clock for clocking the jtag boundary scan sequence. *trst# i v_cpuio jtag test reset: asynchronously resets the tap controller in the processor. *itp(1:0) itp1: prdy itp0: r/s# o i v_cpuio debug port signals: currently defined for the generation of pentium? processors. future uses are not yet defined. * - termination for the itp signals must be done on the system electronics. the intel mobile module does not provide series termination for these signals.
intel pentium? processor with mmx? technology mobile module 15 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.1.8. miscellaneous (44 signals) table 9 lists the intel mobile modules miscellaneous signal pins. table 9. miscellaneous pins name type number description module id o 4 module revision id. these pins track the revision of the intel mobile module. each pin requires a 100k pull up resistor to the switched 3.3v supply. ppp_pp# o 1 pentium ? pro processor or pentium processor present. a high on this signal indicates to the piix4 isa bridge config1 pin that the processor is based on the pentium pro architecture, a low indicates that it is of the pentium processor family. this signal is not connected on pentium pro modules, and grounded on pentium processor modules; the system electronics should provide a 100k pull up to the non-switched 3.3v supply. ground i 32 ground reserved rsvd 7 unallocated reserved pins
intel pentium? processor with mmx? technology mobile module 16 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 2.2. connector pin assignments table 10 lists the signals for each pin of the connector from the intel mobile module to the system electronics. refer to section 2.3 for the pin assignments of the pads on the connector. table 10. connector pin assignments pin# row aa row ab row ba row bb 1 gnd gnd gnd gnd 2 md40 md00 mid0 mid1 3 md41 md04 reserved reserved 4 md42 md02 v_dc v_dc 5 md43 md03 v_dc v_dc 6 v_3s v_3s v_dc v_dc 7 md44 md01 v_dc v_dc 8 md45 md05 v_dc v_dc 9 md46 md06 reserved reserved 10 md47 md07 mid2 mid3 11 gnd gnd gnd gnd 12 cas5#/dqm5 cas0#/dqm0 ad00 frame# 13 cas1#/dqm1 cas2#/dqm2 ad01 lock# 14 ma00 ma01 ad02 devsel# 15 ckea ckeb ad03 irdy# 16 v_3s v_3s v_3s v_3s 17 ma02 ma04 ad04 trdy# 18 ma03 ma05 ad05 stop# 19 md08 md17 ad06 phold# 20 md09 md16 ad07 phlda# 21 gnd gnd gnd gnd 22 md10 md18 ad08 pci_rst# 23 md11 md19 ad09 par 24 md12 md20 ad10 serr# 25 md13 md21 ad11 req0#
intel pentium? processor with mmx? technology mobile module 17 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) table 10. connector pin assignments (continued) pin row aa row ab row ba row bb 26 v_3s v_3s v_3s req1# 27 md14 md22 ad12 req2# 28 md15 md23 ad13 req3# 29 srasa# scasa# ad14 gnt0# 30 srasb# scasb# ad15 gnt1# 31 gnd gnd gnd gnd 32 mwea# mpd0 ad16 gnt2# 33 mweb# mpd4 ad17 gnt3# 34 ras0#/cs0# mpd1 ad18 l2_zz 35 ras1#/cs1# mpd5 ad19 reserved 36 v_3s v_3s v_3s v_3s 37 md36 mpd2 ad20 reserved 38 md39 mpd6 ad21 ppp_pp# 39 md37 mpd3 ad22 clkrun# 40 gnd gnd gnd gnd 41 md35 mpd7 ras2#/cs2# sm_clk 42 md34 md48 ras3#/cs3# sm_data 43 md38 md50 ras4#/cs4# atf_int# 44 md33 md49 ras5#/cs5# susclk 45 v_3s v_3s v_3 v_3 46 md32 md51 ad23 sus_stat# 47 ma06 md52 ad24 v_3 48 ma07 md53 ad25 oem_pu 49 ma08 md54 ad26 vr_on 50 gnd gnd gnd gnd 51 ma09 md55 ad27 vr_pwrgd 52 cas4#/dqm4 cas6#/dqm6 ad28 v_3 53 cas3#/dqm3 cas7#/dqm7 ad29 v_3 54 ma10 ma12 ad30 reserved
intel pentium? processor with mmx? technology mobile module 18 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) table 10. connector pin assignments (continued) pin# row aa row ab row ba row bb 55 v_3s v_3s v_3s reserved 56 ma11 ma13 ad31 init# 57 md25 md56 c/be0# v_cpuio 58 md24 md60 c/be1# intr 59 md26 md58 c/be2# cpurst 60 gnd gnd gnd gnd 61 md27 md57 c/be3# stpclk# 62 md28 md61 ignne# smi# 63 md31 md59 ferr# nmi 64 md30 md62 a20m# v_5 65 md29 md63 v_cpuio v_cpuio 66 v_3s v_3s tdo trst# 67 oem_pd pclk itp0 tdi 68 fqs0 fqs1 itp1 tms 69 hclk1 hclk0 cpu3.3_2.5# tclk 70 gnd gnd gnd gnd note: pins ab54 and ba43 as well as pins ab56 and ba44 are connected together on the intel mobile module. future pcisets will independently drive address and ras signals separately, so caution should be taken when connecting to this interface. 2.3. connector footprint this section contains the 280-pin connector pad assignment. 2.3.1. pin and pad assignment figure 2 shows the connector pad assignments for the manufacturers system electronics. this footprint is viewed from the secondary side of the intel mobile module (the side of the printed circuit board on which the 280-pin connector is soldered). for additional information regarding the orientation of the connector with respect to the system electronics, please contact your local intel sales representative.
intel pentium? processor with mmx? technology mobile module 19 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) aa 70 aa 1 ab 70 ab 1 ba 70 ba 1 bb 70 bb 1 280-pin connector footprint oem pad assignments (viewed from bottom side of processor module) figure 2. 280-pin connector footprint pad numbers, intel mobile module - secondary side 2.4. connector specifications the intel mobile module connector is a surface mount, 0.6 mm pitch, 280-pin connector. there are currently four unique connectors that will be offered by vendors for the intel mobile module. table 11 summarizes some of the more critical specifications for the connector.
intel pentium? processor with mmx? technology mobile module 20 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) table 11. connector specifications parameter condition specification material contact copper alloy housing thermo plastic molded compound: lcp electrical current 0.4 a voltage 50 vac insulation resistance 100m w min. @ 500 vdc termination resistance 20m w max. @ 20mv open circuit with 10ma capacitance 5pf max. per contact mechanical mating cycles 50 cycles connector mating force 0.9n (90gf) max. per contact contact un-mating force 0.1n (10gf) min. per contact 3.0. functional description 3.1. intel mobile module the intel mobile module will support the pentium processor with mmx technology mobile processor running at 166/66, 200/66, 233/66, and 266/66 mhz with 16 kb on-chip code and data cache sizes. 3.2. l2 cache the pentium processor with mmx technology mobile processor's internal cache is complimented with a second-level 2.5v cache using a high- performance pipeline burst sram. the l2 cache can support up to 64 mb of system memory, the maximum amount of cacheable system memory supported by the 430tx pciset system contr oller. the intel mobile module has two 100-pin tsop (thin small outline package) footprints for 512k direct- mapped write-back l2 cache. the intel mobile module supports the zz, or snooze mode power management features in current pipeline burst sram (pbsram). the piix4 isa bridge southbridge component on the system electronics is the source for the generation of zz mode. this zz signal is named l2_zz on the intel mobile module interface, clarifying its sole purpose of zz support for second-level cache. 3.3. 430tx pciset system controller intels 430tx pciset system contr oller is a highly integrated device that combines the mobile pentium processor bus controller, the dram controller, second-level cache controller and pci bus controller into one component. the 430tx pciset has multiple power management features specifically for notebook systems: clkrun# is a feature that enables controlling of the pci clock on or off 430tx pciset suspend modes include suspend to ram (str), suspend to disk (std) and powered on suspend (pos)
intel pentium? processor with mmx? technology mobile module 21 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) system management ram (smram) power management modes include compatible smram (c_smram) and extended smram (e_smram). c_smram is the traditional smram feature implemented in all intel pci chipsets. e_smram is a new feature that supports write-back cacheable smram space up to 1mbyte. to minimize power consumption while the system is idle, the internal 430tx pciset clock is turned off (gated off) when there is no processor and pci activity. the intel mobile module supports only the 430tx pciset features available in the mobile mode of operation. refer to intels latest revision of the 430tx pciset specification for complete details. 3.3.1. memory organization the complete memory interface of the 430tx pciset is available at the intel mobile modules connector; all of the 430tx pciset mobile mode memory configurations and modes of operation are supported. two memory features not supported by the 430tx pciset mobile mode are parity and error detection and correction (edc). dram technologies supported by 430tx pciset include extended data out (edo) and sdram. note the intel mobile module does not support the use of fast page mode (fpm) memory on the system electronics. these memory types may be mixed in the system, but only on a row-by-row basis. in other words, all dram in a particular row (ras[5:0]#) must be of the same technology. the 430tx pciset targets 60ns drams, but also supports 50ns and 70ns components. the intel mobile modules clocking architecture supports the use of sdram. due to the tight timing requirements of 66-mhz sdram clo cks, the clocking mode for sdram or system m anufacturer custom memory configurations allows all host and sdram clocks to be generated from the same physical device on the manufacturers system electronics. driving all of these clo cks out of a s ingle device ensures minimal skew and jitter between clock outputs. for complete details about using sdram memory, and for trace length guidelines, contact your local intel sales representative. for details on memory device support, organization, size and addressing, refer to 430tx pciset documentation and pcd application notes. 3.3.2. 64-mbit sdram support support for 64-mbit sdram memory technology is provided by the 430tx pciset northbridge component. see the 430tx pciset documentation for operational details on how this support is implemented by the component. to provide the equivalent support at the intel mobile module connector and maintain compatibility with future northbridge architectures, the memory signals on the intel mobile module are routed to the connector as shown in figure 3. memory control signals that allow the 430tx pciset to support 64-mbit sdram memory devices are the ras4/ma12 and ras5/ma13. these signals are multiplexed and configurable within the 430tx pciset. figure 3 shows a wiring diagram on the intel mobile module of the ras4/ma12 and ras5/ma13 signals for clarification. proper routing of these signals is required to ensure future intel mobile modules are compatible.
intel pentium? processor with mmx? technology mobile module 22 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) ras4# ras5# ma12 ma13 430tx pciset mmo_002 figure 3. pentium? processor address routing for proper signal routing, the system oem must determine the memory configuration that will be supported during the 430tx pciset generation of intel mobile modules. if the i/o planar is designed to support four banks of memory and 64-mbit sdram memory devices, then the system oem should route the upper two address signals from the intel mobile modules address pins ma[12:13] to the upper order address bits on the sodimm socket and not the ras[4:5]# pins. subsequently if the i/o design supports six banks of memory and does not intend to support 64-mbit memory devices, then ras[4:5]# should be routed from the intel mobile modules ras[4:5]# pins to the sodimm ras pins. even though these two sets of intel mobile module pins are electrically equivalent on the module, connecting the memory address and control signals as suggested will help maintain compatibility with future modules. note the 430tx pciset does not support six banks of memory and 64-mbit sdram devices simultaneously, however, future pcisets may provide this flexibility. to design today for this type of upgrade, it is recommended that q-switches be used on either the ras[4:5]# or ma[12:13] signals, or both. this would ensure that the trace lengths of the ras signals are kept to a minimum, and signal quality is not compromised. 3.3.3. pci interface the 430tx pciset is compliant with the pci 2.1 specification, which improves the worst-case pci bus access latency from earlier pci specifications. the complete pci interface of the 430tx pciset is available at the intel mobile modules connector. the 430tx pciset supports the pci clockrun protocol for power management of pci. in this protocol, pci devices assert the clkrun# open- drain signal when they require the use of the pci interface. (refer to the pci mobile addendum for complete details on the pci clockrun protocol.) the 430tx pciset is responsible for arbitrating the pci bus. when configured in mobile mode, the 430tx pciset can support up to four pci bus masters. there are four pci request/grant pairs, req[3:0]# and gnt[3:0]# available on the connector to the manufacturers system electronics. the 430tx pciset supports only mechanism #1 for accessing pci configuration space, as detailed in the pci specification. this implies that signals ad[31:11] are available for pci idsel signals. however, since the 430tx pciset is always device #0; ad11 will never be asserted during pci configuration cycles as an idsel. thus, ad12 is the first available address line usable as an idsel.
intel pentium? processor with mmx? technology mobile module 23 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 3.4. processor core voltage regulation the intel mobile module supports an input dc voltage range of 5v - 20v (+5 percent) slew-rate controlled from the system battery/power s upply. maximum peak input voltage is 21.1v including ripple. the intel mobile modules dc voltage regulator (dc/dc converter) is designed to support the cpu core voltage and the 2.5v-only cpu interface signals so no special voltage regulation is required on the system electronics. the cpu interface signals between the cpu and piix4 south bridge require proper termination to the v_cpuio (2.5v) power plane and should be treated with special attention. please refer to the signal definitions for recommended resistor termination values. 3.4.1. voltage regulator efficiency the voltage regulator is optimized for pentium processors and is most efficient in the 1a to 3a range. when placed in suspend mode, the module will consume approximately 20mw. see table 12a and 12b for details over the entire current range. table 12a. typical voltage regulator efficiency, vcore = 1.8v (166/200/233 mhz) v_dc (v) i_dc (a) v_5 (v) i_5 (ma) vcore (v) icore (a) vi/o (v) i_i/o (ma) eff. (%) 5 0.429 5.0 13 1.81 1 2.55 52 87 5 0.845 5.0 13 1.81 2 2.55 52 87 5 1.293 5.0 13 1.81 3 2.55 52 85 5 1.776 5.0 13 1.81 4 2.55 52 82 12 0.187 5.0 13 1.82 1 2.55 52 83 12 0.356 5.0 13 1.82 2 2.55 52 86 12 0.54 5.0 13 1.82 3 2.55 52 85 12 0.737 5.0 13 1.82 4 2.55 52 83 18 0.128 5.0 13 1.83 1 2.55 52 82 18 0.244 5.0 13 1.83 2 2.55 52 84 18 0.367 5.0 13 1.83 3 2.55 52 84 18 0.500 5.0 13 1.83 4 2.56 52 82 notes: 1. the above measured efficiencies are typical values from a limited sample size. results may vary across different modules. 2. these efficiencies will change with future voltage regulators that accommodate higher input voltages.
intel pentium? processor with mmx? technology mobile module 24 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) table 13b. typical voltage regulator efficiency, vcore = 2.0v (266 mhz) v_dc (v) i_dc (a) v_5 (v) i_5 (ma) vcore (v) icore (a) vi/o (v) i_i/o (ma) eff. (%) 4.75 0.530 5.0 14 2.00 1 2.52 100 87 4.75 1.032 5.0 14 1.99 2 2.52 100 85 4.75 1.548 5.0 14 1.99 3 2.52 100 84 4.75 2.162 5.0 14 1.99 4 2.52 100 79 12 0.220 5.0 14 2.00 1 2.52 100 83 12 0.415 5.0 14 2.00 2 2.52 100 84 12 0.624 5.0 14 2.00 3 2.52 100 82 12 0.841 5.0 14 1.99 4 2.52 100 81 21 0.128 5.0 14 2.01 1 2.52 100 82 21 0.238 5.0 14 2.00 2 2.52 100 84 21 0.355 5.0 14 2.00 3 2.52 100 83 21 0.478 5.0 41 1.99 4 2.52 100 81 notes: 1. the above measured efficiencies are typical values from a limited sample size. results may vary across different modules. 2. these efficiencies will change with future voltage regulators that accommodate higher input voltages. 3.4.2. voltage regulator control the vr_on pin on the connector allows a digital signal (3.3v, 5v safe) to control the voltage regulator. the system m anufacturer can use this signal to turn the intel mobile modules voltage regulator on or off. vr_on should be controlled with the same digital control signal used to control the systems switc hed 3.3v power planes. the piix4 south bridge defines suspend b as the power management state in which power is physically removed from the processor, l2 cache, 430tx pciset, and voltage regulator. in this state, the susb# pin on the piix4 isa bridge controls these power planes. from the assertion of vr_on, the voltage regulator has a turn-on time latency of approximately 6ms. in order to bring both the processors core and i/o ring voltages up together, the system m anufacturer must ensure that the systems switc hed 3.3v supply (voltage plane v_3s) turns on and off with the intel mobile modules core voltage. this requires properly sequencing of the systems volt age regulator and the vr_on signal as shown in figure 4.
intel pentium? processor with mmx? technology mobile module 25 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 3.4.3. voltage signal definition and sequencing table 14. voltage signal definitions and sequences signal source definitions and sequences v_dc system electronics dc voltage driven from the power supply and is required to be between 5v and 20v dc +5% (maximum peak voltage is 21.1v including ripple). v_dc powers the intel mobile modules dc-to-dc converter for processor core and i/o voltages. caution: the intel mobile module must not be inserted or removed while v_dc is powered on. v_3 system electronics v_3 is supplied by the system electronics; the mtxc uses it during the suspend to dram state. v_5 system electronics v_5 is supplied by the system electronics. it is used by the intel mobile modules voltage regulator. v_3s system electronics v_3s are supplied by the system electronics for the processor, mtxc, and cache devices. each must be powered off during system suspend-to-dram and suspend-to-disk states, typically this signal is switched by a fet switch. vr_on system electronics this 3.3v signal controls the operation of the intel mobile modules voltage regulator. this signal should be generated as a function of the piix4 susb# signal. vr_on should be timed to rise after the switch power planes have stabilized. please refer to section 3.4.2 for proper vr_on sequencing. note: the system electronics should subtract 6ms for the maximum latency of vr_on to v_core of the voltage regulator on the intel mobile module. v_core intel mobile module only a result of vr_on being asserted, v_core is an output of the dc-dc regulator on the intel mobile module and is driven to the appropriate voltage level of the processor: 1.8 or 2.0. vr_pwrgd intel mobile module only upon sampling the voltage level of v_core for the processor, minus tolerances for ripple, vr_pwrgd is driven active high (3.3v) for the system electronics to sample prior to providing pwrok to the piix4. if vr_pwrgd is not sampled active within 1 second of the assertion of vr_on the system electronics should deassert vr_on. caution : this signal has an output impedance of approximately 100k w . care must be taken to prevent loading of this signal. v_cpuio intel mobile module only v_cpuio is 2.5v. the system electronics uses this voltage to power the piix4- to-processor interface circuitry, as well as the hclk_(0:1) drivers for the sdram/oem processor clock.
intel pentium? processor with mmx? technology mobile module 26 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) voltage plane sequencing v_dc 1. pwrok on system electronics should be active on when vr_pwrgd is active and v_3s is good. 2. cpu_rst from system electronics should be active for a minimum of 6 ms after pwrok is active and pll_stp# and cpu_stp# are inactive. note that pll_stp# is an and condition of rsmrst# and susb# on the piix4. 3. v_dc >= 4.7v, v_5>=4.5v, v_3s>=3.0v. 4. this is the 5v power supplied to the intel mobile module connector. this should be the first 5v plane to power up. v_3 v_5 vr_pwrgd v_3s vr_on 0 ms min 0 ms min 0 ms min 6 ms max note 3 v_cpuio see note 4 figure 4. power on sequence timing figure 4 details the sequencing of signals and voltage planes required for normal operation of the intel mobile module. the intel mobile module also provides the vr_pwrgd signal, which indicates that the voltage regulator power is operating at a stable voltage level. the system m anufacturer should use this signal on the system electronics to control power inputs, and gate pwrok to the piix4 south bridge. please contact your local intel sales representative for more details about the voltage regulator, power sequencing, and proper voltage signaling. 3.5. active thermal feedback table 15 identifies three addresses allocated for the system management bus (smbus) on the intel mobile module. two of these addresses are reserved for future use. table 15. lm75 smbus address table function fixed address ad bits (6:3) selectable address ad bits (2:0) lm75 thermal sensor 1001 000 reserved 1001 001 reserved 1001 010 notes: the lm75 is not electrically compatible with smbus addressing. the 4-bit fixed address used by the lm75 is currently invalid under revision 1.0 of the system management bus specification from intel. after consulting your local intel sales representative, refer to the datasheet for the lm75 digital thermometer for complete device programming details.
intel pentium? processor with mmx? technology mobile module 27 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 3.6. thermal transfer plate the intel mobile module provides a thermal transfer plate connected to the processor in a standard position called the thermal attach point. the thermal attach point is a fixed location relative to the mounting holes and other physical datum on the intel mobile module. the system m anufacturer can use both a heat pipe and a heat spreader plate in contact with the thermal attach point to transfer heat through the notebook system. the thermal transfer plate is physically mounted to the intel mobile module, and may be different from one generation of intel mobile module to the next. however, the thermal attach point will remain fixed across future generations of intel mobile modules. figure 5 shows the conceptual relationship between the circuit board, thermal transfer plate and thermal attach point. 3.7. module thermal resistance intel has completed extensive thermal testing of the module in a variety of environments to determine the overall thermal resistance between the cpu tcp packaging and the top of the ttp. the worst case thermal resistance guaranteed by intel is 2.5 c/w though typically this resistance will be less. system oems should take this under consideration when designing system thermal solutions. 4.0. mechanical requirements 4.1. module dimensions this section provides the physical dimensions for the intel mobile module. 4.1.1. board area figure 6 shows the board dimensions and the connector orientation for the intel mobile module . these dimensions are necessary to accommodate the next generation of intel mobile processor and pci northbridge chipset controller.
intel pentium? processor with mmx? technology mobile module 28 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) figure 5. intel mobile module thermal transfer plate
intel pentium? processor with mmx? technology mobile module 29 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) figure 6. board dimensions with 280-pin connector orientation
intel pentium? processor with mmx? technology mobile module 30 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 4.1.2. printed circuit board thickness figure 7 shows the intel mobile module profile and the associated minimum and maximum thickness of the printed circuit board (pcb). the range of pcb thickness allows for different pcb technologies to be used with current and future modules. note the system m anufacturer must ensure that the mechanical restraining method and/or system-level emi contacts are able to support this range of pcb thickness, to ensure compatibility with future modules. 4.1.3. height restrictions figure 8 shows the intel mobile module mechanical stackup and associated component clearance requirements. this "block" represents the volume that may be occupied by components on the various versions of the processor module. the oem system s hould be defined so that no part of the system w ill intrude into this volume, which may result in part-to-part interference. the system m anufacturer establishes the board- to-board clearance between the intel mobile module and the system electronics by selecting one of three possible mating connectors. the mating connectors provide board-to-board clearance distances of 4 mm, 6 mm or 8 mm. with these three options, the system m anufacturer has reasonable flexibility in choosing components on the system electronics that are between the two boards. note the intel mobile module top side component clearance is referenced from the bottom of the pcb, so it is independent of the pcb thickness. figure 8 shows the module volume assuming a 4mm board-to-board connector. when using the 4mm connector, 2mm of the connector height extends beyond the module volume shown in figure 8. if the 6mm board-to-board connector is used on the system electronics, then 4mm extends beyond the module keep-out volume. if using the 8mm connector, 6mm will extend beyond the module keep-out volume. intel mobile module printed circuit board .070" maximum .057" minimum figure 7. pcb board thickness
intel pentium? processor with mmx? technology mobile module 31 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) figure 8. 3-d mechanical drawing
intel pentium? processor with mmx? technology mobile module 32 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 4.2. module physical support figure 9 shows the intel mobile module standoff support hole patterns and the board edge clearance around the perimeter of the module. these hole locations and board edge clearances will remain fixed for all intel mobile modules. the hole patterns and board edge clearance lets the system m anufacturer develop several methods for mechanically supporting the intel mobile module within a particular notebook system. hole detail, 3 places standoff holes and board edge keepouts (top side) 0.762mm width of emi containment ring 1.27mm board edge to emi ring 2.54mm keepout area 3.81+/-0.19mm board edge to hole centerline 3.81+/-0.19mm 4.45mm diameter grounded ring 2.40mm +/- 0.3mm hole diameter mmo_009 figure 9. standoff holes, board edge clearance and emi containment ring the board edge clearance includes a 0.762 mm (0.030 in) width emi containment ring around the perimeter of the module. this ring is on each layer of the module pcb and is grounded. on the surface of the module, the metal is exposed for emi shielding purposes. the hole patterns placed on the module also have a plated surrounding ring and one can use a metal standoff to contact the ring for emi shielding purposes. figure 9 shows the dimensions of the emi containment ring and the keepout area. no components are placed on the board in the keepout area. 4.3. module mounting requirements three mounting holes are available to the system oem for securing the module to the system base or the system electronics. see figure 6 for relative hole placements. it is strongly recommended the system oem utilize mounting screws through all three of these holes to ensure long term reliability of the mechanical and emi integrity of the system.
intel pentium? processor with mmx? technology mobile module 33 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) to interface to the module's thermal transfer plate (ttp), it is recommended that the exact dimensions shown in figure 10 for the oem thermal interface block be used. these dimensions provide maximum contact area to the ttp while ensuring that no warpage of the ttp occurs. if warpage occurs, due to the use of an improperly- designed interface, or over-tightening of assembly screws, the thermal resistance of the module could be adversely affected. when attaching the mating block to the module ttp, material such as a thermal elastimer or thermal grease should be used. this material is designed to reduce the thermal resistance and should be placed between the ttp and the oem mating block. this will improve the overall system thermal efficiency. once the oem has placed the mating thermal transfer plate, secure it with 2.0mm screws using a maximum torque of 1.5 - 2.0 kg*cm (equivalent to 0.147 - .197 n*m) figure 10. ttp interface block dimensions
intel pentium? processor with mmx? technology mobile module 34 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 4.4. module product tracking code the intel mobile module incorporates a product tracking code (ptc) for oems to inspect module speed, cache size, and revision. the ptc is etched on the secondary side of the module to the right of the product id matrix label as shown in figure 11. the ptc consists of thirteen characters defined by: pmcaaabbcccdd where: pmc - intel mobile module on .25 micron aaa - processor frequency (166/200/233/266 mhz) bb - cache size (00-no cache, 02-256k, 05-512k) ccc - design revision (start at 001) dd - processor revision (start at aa) figure 11. product tracking code intel assembly identification intel serial number product trackin g code
intel pentium? processor with mmx? technology mobile module 35 1/8/98 4:35 pm 24351502.doc intel confidential (until publication date) 5.0. environmental standards table 16 lists the intel mobile modules environmental standards. table 16. environmental standards parameter condition specification temperature non-operating -40 c to 70 c operating 0 c to 55 c humidity 95% relative humidity @ 30 c voltage v_dc +/- 5% v_3s +/- 5% v_3 +/- 5% shock operating half sine, 2g, 11msec unpackaged trapezoidal, 30g, 11msec packaged inclined impact @5.7ft/s packaged half sine, 2msec @42 simulated free fall vibration unpackaged 5hz to 500hz 2.2grms random packaged 10hz to 500hz 1.0grms packaged 11,800 impacts 2hz to 5hz (low frequency) esd air discharge 0 to 2kv (no detectable err) 0 to 8kv (no intermittent err) 0 to 20kv (no hard failures)
united states, intel corporation 2200 mission college blvd., p.o. box 58119, santa clara, ca 95052-8119 tel: +1 408 765-8080 japan, intel japan k.k. 5-6 tokodai, tsukuba-shi, ibaraki-ken 300-26 tel: + 81-29847-8522 france, intel corporation s.a.r.l. 1, quai de grenelle, 75015 paris tel: +33 1-45717171 united kingdom, intel corporation (u.k.) ltd. pipers way, swindon, wiltshire, england sn3 1rj tel: +44 1-793-641440 germany, intel gmbh dornacher strasse 1 85622 feldkirchen/ muenchen tel: +49 89/99143-0 hong kong, intel semiconductor ltd. 32/f two pacific place, 88 queensway, central tel: +852 2844-4555 canada, intel semiconductor of canada, ltd. 190 attwell drive, suite 500 rexdale, ontario m9w 6h8 tel: +416 675-2438

▲Up To Search▲

Price & Availability of INTELPENTIUMCPU

	To Download INTELPENTIUMCPU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .